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Software defined radio (SDR) is a method to design radio frequency (RF) signal systems using software to implement radio components that are normally implemented in hardware. Several examples of components that can be designed in SDR include RF signal filters, signal amplifiers, and signal resamplers. SDR applications include amateur radio transmission, aircraft and ship tracking, RF communications, and radio astronomy, to name a few. A great advantage of implementing a RF system in software is that the system developed in software is more flexible and upgradeable than a system designed with hardware alone.
QRC Technologies offers a wide range of software defined radio solutions and have provided their Wide-Band Transcorder (WBT) platform for this project. QRC would like for its customers to be able to develop custom applications on the WBT with limited programming and communication expertise. One solution to this challenge is to leverage the free and open source GNU Radio Companion (GRC) software development kit. GRC uses a graphical programming concept that users can easily comprehend and become proficient in. The goal of this project include the creation of several GRC programming blocks that encapsulate WBT SDR functions.
The blocks that were developed that are of interest to our sponsor, QRC, are a GPS Source block that outputs metadata such as Latitude, Longitude, and time; an fast Fourier transform (FFT) Source block that accesses the pre-processed FFT data available on the WBT and provides an output for the data; a Sweeper block which performs many small FFTs and concatenates them to produce a spectrum with lower noise; an FPGA based HA block that performs a FFT on IQ data; and we partially completed a block which takes in IQ data and writes them in an industry standard VRT file that can be read by the WBT.
In addition to implementing the WBT’s functionality in GRC blocks, the team has also investigated the feasibility of increasing the speed of these blocks using a hardware accelerator (HA). Specifically, a HA was developed for a fundamental mathematical signal calculation: the FFT. The FFT HA was developed on a field-programmable gate array (FPGA) which is an integrated circuit that is able to be configured to implement digital logic. The usage of a FPGA allowed the team to exploit the parallel nature of the FPGA and thereby greatly improve the performance of this calculation in a GRC application. Please reference Figure 1 below for the HA data flow.
The team was able to successfully implement four GRC blocks that are now available to be included in customs applications developed for the WBT. A FFT HA was also successfully developed and included in a GRC block. The FFT HA is able to process up to 8192 points in one FFT cycle and has latency of approximately 330 μseconds to process 8192 points.
Electrical and computer engineering, Software Defined Radio, GNU Radio Companion, FPGA, Hardware Accelerator
Electrical and Computer Engineering | Engineering
Dr. Ruixin Niu
Dr. Carl Elks
VCU Capstone Design Expo Posters
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