Defense Date
2024
Document Type
Dissertation
Degree Name
Doctor of Philosophy
Department
Electrical & Computer Engineering
First Advisor
Carl Elks, Ph.D.
Abstract
Cyber-Physical systems are becoming more and more prevalent in our society and are simultaneously becoming more complex due to evolving technological capabilities in both hardware and software. This complexity exacerbates verification and validation activities thereby negatively impacting important system attributes like design assurance, system reliability, development costs and trust. These facts necessitate the need for computing architectures that constrain complexity for the sake of assurance. Traditional software and hardware development for safety-critical systems have been demonstrated in previous safety-critical systems and the established development methodologies are well understood. However, both technologies have their strengths and limitations. Processor-based technology (SW based computing) is optimized for flexibility allowing the end user to realize just about anything by writing Software to accomplish the needed functionality. The drawback of processor-based technology is that a large degree of complexity can is introduced in the system. This complexity first manifests itself in software-based computing at the bottom of the software stack beginning with the expansive capabilities and performance of many component general-purpose COTS microprocessors. From here, the stack only gets more complex with operating systems, middleware, supporting functions, and finally, applications sitting at the top of the stack. In contrast, if the hardware approach is adopted, a different complexity is observed in the form of lengthy development cycles, proprietary tool sets, and specialized skills that are diminishing in the workforce. To bridge the gap between these two development workflows, this research seeks to explore a middle ground in computing that rests between software and hardware development: FPGA overlays. FPGA overlays are not a new technology but their application to the safety-critical and the dependable computing world has not been largely adopted. Furthermore, dependable FPGA overlays in current research are targeted to improve the reliability of a single chip and fail in single point of failure analysis since if a single FPGA chip fails, the system fails. This work seeks to characterize and add to the knowledge base of high assurance system design through the exploration and characterization of an architecture that minimizes the complexity of individual system nodes and, subsequently, the resulting system complexity.
Rights
© Richard Hite
Is Part Of
VCU University Archives
Is Part Of
VCU Theses and Dissertations
Date of Submission
8-8-2024