Defense Date
2025
Document Type
Thesis
First Advisor
Dr. Jayasimha Atulasimha
Abstract
This thesis presents an efficient implementation of a quantized autoencoder for anomaly detection on Field-Programmable Gate Array (FPGA) platforms. We explore the challenges and tradeoffs in migrating from a theoretical model to a hardware constrained implementation. The autoencoder employs a training methodology to limit compute resource and power requirements while maintaining detection accuracy. We detail the implementation process using a High-Level Synthesis (HLS) workflow, first on a resource constrained, less sophisticated platform and then on a relatively higher performance platform. Resource optimization techniques were analyzed and implemented to maximize reduction in latency while managing the FPGA resource budget. Experimental results show that the more sophisticated platform implementation achieves a detection accuracy negligibly lower than a traditional computer hardware implementation baseline, while delivering a sizeable speedup compared to the less sophisticated platform implementation and an even more significant speedup over the baseline execution. Furthermore, our implementation demonstrates significant power efficiency with reduction in power consumption by one and two orders of magnitude for the more sophisticated and less sophisticated platforms respectively compared to the baseline execution. The findings demonstrate that quantized neural networks can be effectively deployed on mid-range FPGA platforms for real time anomaly detection in resource constrained edge environments.
Rights
© The Author
Is Part Of
VCU University Archives
Is Part Of
VCU Theses and Dissertations
Date of Submission
4-30-2026